Adders and multipliers are logical elements that perform basic digital numerical operations in digital processors such as microprocessors, digital signal processors (“DSPs”), arithmetic logic units (“ALUs”), hardware accelerators (“HACs”), etc. The overall performance of such devices is generally dependent on the speed and energy efficiency of its constituent logical elements. Adders, multipliers, and other logical elements are generally required to perform floating-point calculations, which inherently increase their complexity. The cost of microprocessors, DSPs, etc., is substantially proportional to the silicon area required to implement the logical elements from which they are formed. Thus, the design of adders, multipliers, etc., is an important consideration in providing a competitive design for an end product, and any improvement in efficiency and reduction in silicon area required for implementation can have a substantial impact on market acceptance. A particular concern is reducing the bit width of arithmetic registers.
The ability to improve the performance and reduce the silicon area required to implement ALUs, HACs, etc., without incurring unnecessary cost would answer an important market need.